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AD9985A
09
7–0 Green Channel Gain Adjust (GREENGAIN)
MODE CONTROL 1
An 8-bit word that sets the gain of the green channel.
See REDGAIN (08).
0E
7 Hsync Input Polarity Override
This register is used to override the internal circuitry
0A
7–0 Blue Channel Gain Adjust (BLUEGAIN)
An 8-bit word that sets the gain of the blue channel.
See REDGAIN (08).
that determines the polarity of the Hsync signal going
into the PLL.
Table 13. Hsync Input Polarity Override Settings
INPUT OFFSET
Override
Result
0B
7–1 Red Channel Offset Adjust
This offset register and those that follow have two
modes of operation. One mode is when the auto offset
function is turned off (manual mode) and the other is
when auto offset is turned on.
0
1
0E
Hsync polarity determined by chip
Hsync polarity determined by user
The default for Hsync polarity override is 0 (polarity
determined by chip).
6 HSPOL Hsync Input Polarity
When in manual offset adjustment mode (auto offset
turned off), this register behaves exactly like the
AD9883A. It is a 7-bit offset binary word that sets the
dc offset of the red channel. One LSB of offset
adjustment equals approximately one LSB change in
the ADC offset. Therefore, the absolute magnitude of
the offset adjustment scales as the gain of the channel
is changed. A nominal setting of 63 results in the
channel nominally clamping the back porch (during
the clamping interval) to Code 00. An offset setting of
127 results in the channel clamping to Code 64 of the
ADC. An offset setting of 0 clamps to Code –63 (off
the bottom of the range). Increasing the value of red
offset decreases the brightness of the channel.
When in auto offset mode, the value in this register is
digitally added to the red channel ADC output. The
purpose of doing this is to match the operation with
manual offset adjustment. Adjusting these registers is
an easy way to make brightness adjustments.
Although some signal range is lost with this method, it
A bit that must be set to indicate the polarity of the
Hsync signal that is applied to the PLL Hsync input.
Table 14. Hsync Input Polarity Settings
Polarity Result
0 Active low
1 Active high (power-up default)
Active low means the leading edge of the Hsync pulse
is negative-going. All timing is based on the leading
edge of Hsync, which is the falling edge. The rising
edge has no effect.
Active high is inverted from the traditional Hsync,
with a positive-going pulse. This means that timing is
based on the leading edge of Hsync, which is now the
rising edge.
The device operates if this bit is set incorrectly, but the
internally generated clamp position, as established by
clamp placement (Register 0x05), is not placed as
expected, which can generate clamping errors.
has proven to be a very popular function. In order to
be able to increase and decrease brightness, the values
in these registers in this mode are signed twos comple-
ment (vs. manual mode, where the values in this
register are binary). The digital adder is used only in
auto offset mode. Although it cannot be disabled,
0E
5 Hsync Output Polarity
This bit determines the polarity of the Hsync output
and the SOG output . Table 15 shows the effect of this
option. SYNC indicates the logic state of the sync
pulse.
setting this register to all 0s effectively disables it by
Table 15. Hsync Output Polarity Settings
always adding 0.
Polarity
Result
0C
7–1 Green Channel Offset Adjust
This register works exactly like the Red Channel
Offset Adjust Register (0x0B), except it is for the green
channel.
0
1
0E
Logic 1 (positive polarity; power-up default)
Logic 0 (negative polarity)
4 Active Hsync Override
This bit is used to override the automatic Hsync
selection. To override, set this bit to Logic 1. When
0D
7–1 Blue Channel Offset Adjust
This register works exactly like the Red Channel
Offset Adjust register (0x0B), except it is for the blue
channel.
Rev. 0 | Page 21 of 32
overriding, the active Hsync is set via Bit 3 in this
register.
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